University of Bahrain
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Optimizing State Space Integral Controllers for DC-DC Buck Converters Using FPGA-Based Genetic Algorithms

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dc.contributor.author K. Namboothiripad, Mini
dc.date.accessioned 2024-06-05T15:01:16Z
dc.date.available 2024-06-05T15:01:16Z
dc.date.issued 2024-06-05
dc.identifier.issn 2210-142X
dc.identifier.uri https://journal.uob.edu.bh:443/handle/123456789/5732
dc.description.abstract The state space integral controller approach is highly effective for precise and efficient voltage control of DC-DC buck converters, which are crucial in a wide range of applications. This paper presents strategies for implementing a Genetic Algorithm (GA) to tune the gain parameters of a state feedback controller with integral action using FPGA technology. The GA optimizes controller gains to achieve desired dynamic performance and zero steady-state error under multiple constraints. By leveraging the parallel processing capabilities of FPGAs, the GA’s parallel behavior can be effectively utilized to accelerate computations. We implemented the GA on a PYNQ-Z2 SoC FPGA using Vivado high-level synthesis tools, starting with a population of 12 solutions and running for 20 iterations. Our results show that the GA effectively tunes gains to meet various overshoot and settling time requirements while maintaining zero steady-state error. Additionally, we observed a 5.3-fold speed-up in execution with our 100 MHz customized design compared to the 650 MHz ARM processor. By using an FPGA board with more resources, the design clock frequency and thus the throughput and acceleration could be improved further. Integrating GA with FPGA technology significantly reduces the latency for computation making it highly beneficial for any GA based real-time applications. en_US
dc.language.iso en en_US
dc.publisher University of Bahrain en_US
dc.subject Buck Converter, FPGA, Genetic Algorithm, High Level Synthesis, State Space Integral Controller, Vivado Tools en_US
dc.title Optimizing State Space Integral Controllers for DC-DC Buck Converters Using FPGA-Based Genetic Algorithms en_US
dc.identifier.doi http://dx.doi.org/10.12785/ijcds/XXXXXX
dc.volume 16 en_US
dc.issue 1 en_US
dc.pagestart 1 en_US
dc.pageend 11 en_US
dc.contributor.authorcountry India en_US
dc.contributor.authoraffiliation Department of Electrical Engineering, Agnel Charities’ Fr. C. Rodrigues Institute of Technology en_US
dc.source.title International Journal of Computing and Digital Systems en_US
dc.abbreviatedsourcetitle IJCDS en_US


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