FPGA-Based MWD for Network Error Correction

Abstract

This paper presents reconfigurable hardware architecture for MWD (Minimum Weight Decoding) algorithm for network error correction, with high throughput on Field Programmable Gate Array (FPGA). Network Error Correction (NEC) is used for detecting and correcting the errors in noisy communication channels when multicasting a source message to a set of nodes. Minimum Weight Decoding (MWD) algorithm is a cyclic linear block codes that are used as Forward Error Correcting (FEC) codes. The design can be reconfigured for different message length and different generator number, the encoder and decoder has been described using VHDL (VHSIC Hardware Description Language). The decoder has the ability to detect and correct different types and different numbers of errors based on the message length and the length of redundant data. The design has been simulated and tested using ModelSim PE student edition 10.4. Spartan 3 FPGA starter kit from Xilinx has been used for implementing and testing the design in a hardware level.