University of Bahrain
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SPIMN Stateful Packet Inspection for Multi Gigabits Networks

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dc.contributor.author Ibrahim,Amr
dc.date.accessioned 2018-07-31T08:43:07Z
dc.date.available 2018-07-31T08:43:07Z
dc.date.issued 2017-05
dc.identifier.issn 2210-1519
dc.identifier.uri https://journal.uob.edu.bh:443/handle/123456789/1729
dc.description.abstract Stateful Packet Inspection (SPI) is the most important area of Network Intrusion Detection Systems (NIDS (However it must be operated in multi-Gigabit speeds, to trace and reassemble every connection, and examine every packet flow. I proposed Stateful Packet Inspection for Multi Gigabits Networks (SPIMN). It is customized hardware to achieve a more efficient and faster online inspection system. A generic architecture of SPIMN is based on using FPGA and Header Inspection. Therefore, Xilinx ISE 14.1 used in the design and in the simulation to test the design before the implementation on FPGA Virtex-7 by creating a Test-bench circuit. Finally, the testing and evaluation of SPIMN indicate that this model can work with more than 2,000 Snort rules on 100 Gigabit Ethernet networks. en_US
dc.language.iso en en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-ShareAlike 4.0 International *
dc.rights.uri http://creativecommons.org/licenses/by-nc-sa/4.0/ *
dc.subject Stateful Packet Inspection (SPI)
dc.subject Header Inspection
dc.subject Header Parser
dc.subject Packet Reassembly
dc.subject Field Programmable Gate Array (FPGA)
dc.title SPIMN Stateful Packet Inspection for Multi Gigabits Networks en_US
dc.type Article en_US
dc.identifier.doi http://dx.doi.org/10.12785/IJCNT/050205
dc.volume 05
dc.issue 02
dc.pagestart 77
dc.pageend 88
dc.source.title International Journal of Computing and Network Technology
dc.abbreviatedsourcetitle IJCNT


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