Abstract:
A novel AXI interconnect-based Network-on-Chip (NoC) architecture is presented in this
research. The purpose of the architecture is to make System-on-Chip (SoC) designs more efficient
by reducing latency and improving throughput. Because of its high performance and bandwidth
capabilities, the Advanced eXtensible Interface (AXI), which is a component of the Advanced
Microcontroller Bus Architecture (AMBA) of the ARM architecture, is used. This configuration
makes it possible to communicate effectively inside the chip. The proposed architecture overcomes
the scalability limits that are inherent in conventional bus systems. This is accomplished by
integrating AXI with NoC principles, which enables more efficient data transmission over a greater
number of linked modules. By introducing an effective routing system and a network interface that
has been improved, This research work enables packet transfer to occur without interruption. A
2x2 mesh topology is used to simulate the proposed architecture, and an XY routing algorithm is
included into the simulation in order to guarantee that deadlock and livelock-free operations are
carried out. This highlights the potential of the proposed architecture in high-performance
computing applications that require rapid data exchange and minimal response times. The
simulation results demonstrate significant improvements over traditional interconnect approaches,
yielding a lower latency of 0.99 microseconds and a higher throughput of 4.363 flits per cycle
which demonstrates the potential of the proposed architecture.
