Abstract:
This research introduces a novel Network-on-Chip (NoC) architecture based on AXI interconnect as an SoC optimization method to reduce latency and improve throughput. AMBA architecture allows efficient intra-chip communication. Integrating the AXI with NoC principles provides a scalable solution for efficient data transmission across multiple connected modules, which is difficult to achieve in traditional bus systems. Some notable innovations include efficient routing mechanisms and a better network interface that enables the smooth transfer of packets. Simulations show that a 2x2 mesh network with XY routing can achieve latency as low as 0.99 μs, which has an effective throughput of up to 4.363 flits per cycle, making the architecture viable for high-performance computing applications at scale.