Cell Optimization and Realization of Vedic Multiplier Desing in QCA

Abstract

The construction of devices with smaller sizes, lower power dissipation, and higher speeds is a significant problem in contemporary computational technology. Technology advancement is required to get improved power dissipation, size, and speed optimization. By incorporating numerous architectural and behavioural alterations in the current technologies, researchers are attempting to identify ways and means. Designing digital circuits based on reversible logic and implementing them in quantum cellular automata is one such potential approach (QCA). The propagation delay in a multiplication operation is mostly caused by the addition of partial products and the production of partial products. This study proposes a Vedic multiplier based on UrdhwaTriyakbhyam. It has been found that the suggested designs of a Half Adder, 4-bit Ripple Carry Adder, 2×2 Vedic Multiplier, followed by 4×4 Vedic Multiplier and 8×8 Vedic Multiplier circuits have resulted in reductions of 68.75%, 72.64%, 44.84%, 43.44%, and 60.00% in the circuit size, respectively. When compared to previously proposed circuits, improvements in the area have also been observed, with increases of 57.14%, 55.55%, 48.45%, 28.03%, and 42.57% in the area of the Half Adder Circuit, 2×2 Vedic Multiplier, 4-bit Ripple Carry Adder, 4×4 Vedic Multiplier, and 8×8 Vedic Multiplier circuits, respectively. Numerous parameters like area, clock latency, and quantum cost were calculated using the QCAD tool.