Introduction to Special Issue: Design and Performance of Networks on Chip

Abstract

This special issue of International Journal of Computing and Digital Systems (IJCDS) focuses on Design and Performance of Networks on Chip, and publishes selected papers from the 2nd International Workshop on Design and Performance of Networks on Chip (DPNoC 2015), which has been held on August 17-20, 2015, Belfort, France [1, 2], and was organized in conjunction with the 10th International Conference on Future Networks and Communications (FNC 2015) [3]. This workshop represented an international forum for researchers from both academia and industry to expose the latest trends, research findings, and emerging issues in the on-chip networking area and its design and performance. The first International Workshop on the Design and Performance of Networks on Chip (DPNoC 2014) was held on August 17-20, 2014, Niagara Falls, Ontario, Canada [4, 5]. The international workshop DPNoC'2014 was organized in conjunction with the 9th International Conference on Future Networks and Communications, Niagara Falls, Ontario, Canada, August 17-20, 2014 [6]. The DPNoC 2015 workshop has attracted papers from authors from several countries across the world. Each paper was reviewed by the members of program committee. The accepted papers cover a range of topics related to the theme of DPNoC 2015. From the conference accepted papers, only five have been selected to be submitted as extended versions in the special issue on Design and Performance of Networks on Chip in the journal special issue, in addition to one more paper selected from normal submission to the IJCDS journal.