An efficient carry save multiplier for signal processing applications

Abstract

The technique used in the addition of partial products has a big impact on multiplier performance. Two novel contributions proposed in this work. The first novel contribution proposes a modified vector merging adder that has less latency, power and hardware complexity than the existing adder, and the second contribution is a multiplexer-based full adder which has better area efficiency. This work focuses on achieving efficient carry save multiplication through the use of the proposed modified vector merging adder. The goal of this work is to create an efficient vector merging adder and to modify the design of an enhanced full adder used in the Carry Save Multiplier(CSM) architecture to produce a final product with less latency, power and hardware complexity. The modified vector merging adder and multiplexer-based full adder provides an efficient design of carry save multiplier when compared to the use of enhanced full adder technique. Xilinx ISE Design 14.7 version is used for the design and synthesis.