Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ

Abstract

When the technical node progresses into the deep submicron area, one of the main challenges with CMOS technology is the increase in power dissipation. Due to its non-volatility, high speed, high durability, CMOS compatibility, and, most crucially, low power consumption, the Spin transfer torque (STT) switching mechanism based on Magnetic tunnel Junction (MTJ) is acknowledged as one of the most promising spintronic devices for the post-CMOS era. In this study, we suggest a new Arithmetic logic unit technique based on the fusion of STT and SHE aided CMOS circuits. When compared to DPTL-C2MOS-ALU and P-MALU, the simulation results demonstrated a significant reduction in power and area utilisation. All simulation results indicate that the suggested design outperforms the other ALU designs in terms of power consumption, delay, and device count. Electrical simulations are used to demonstrate the proposed design's viability in VLSI circuits by demonstrating its capabilities for higher bit operations