Design and Analysis of Efficient Vedic Multiplier for Fast Computing Applications

Abstract

The significant part of every digital signal processing (DSP) application is a multiplier. This work presents the high performance 4x4 and 8x8 Vedic multiplier designed utilizing scalable adder and compressor architectures. Several 8-bit adder designs, namely CPL, GDI 1, and Scalable full adders, are implemented to establish the superiority of the Scalable adder, which is used for compressor implementation. The proposed 4x4 Vedic Multiplier architecture, comprises half adder, a chain of 3-2 compressors, and a chain of 4-2 compressors. The design metrics are compared to existing Binary, Braun, and Array multipliers, as well as five standard Vedic multiplier designs. This 4x4 multiplier is compared under similar conditions with eight other multiplier topologies, and the proposed 4x4 Vedic multiplier provides the best performance considering the power, delay, PDP and EDP of the circuits. The proposed 4x4 Vedic multiplier is extended to an 8x8 Vedic multiplier design and its performance analysis is done. All circuits are implemented using Cadence Virtuoso simulation software at 45-nm technology. Monte Carlo simulations and process corner analysis of the proposed design are also done. The overall results of the proposed design show that it is speed-efficient and consumes less power, thus making it relevant for fast computing applications such as image processing.