Degradation of MOS parameter due to Bias Instability

Abstract

Aggressive integrated circuits dimension scaling while the supply voltage is not proportionally scaled leads to reliability degradation. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) effect for planner MOS transistor is two primary bottlenecks of the oxide wear-out phase. The lifetime of the devices is truncated by the failure mechanism caused by the aging effect of devices. The accumulation of additional charges into the oxide dielectric and Si-SiO2 interface, result in a shift into threshold voltage, mobility degradation, and oxide breakdown, shows prominent degradation into NMOS due to hot carrier injection (HCI) and into PMOS due to negative bias temperature instability (NBTI) as a function of applied electrical stress, stress time, and temperature. The AC voltage stress is lower compared to DC voltage stress, more carrier diffuses to interface at higher voltage, lower thickness, and higher temperature results in a larger shift in the threshold. The lifetime of a device with a continuous supply of higher voltage leads to degradation with the scaling factor. In this work the numerical simulation of HCI and NBTI impact over MOS parameter degradation explored and found that shift caused by NBTI can be annealed with time, HCI cannot be annealed.