VLSI Architectures of Booth Multiplication Algorithms – A Review

Abstract

The Booth multiplication scheme plays a major role in designing signed multiplier using multiplier encoder and by decreasing the number of intermediate products. Both radix-4 and radix-8 Booth encoding schemes are widely used due to simple and fast respectively. Multiplier is one of the basic as well as an important part in arithmetic unit of many high- performance operations like digital signal processing (DSP) and digital image processing (DIP) and other high-performance central processing unit (CPU) operation. In the past decade numerous ways of Booth multiplier circuits have been implemented by using different application specific integrated circuit (ASIC) technology like Taiwan semiconductor manufacturing technology (TSMC) 45 nm and 65 nm complementary metal oxide semiconductor (CMOS) process and some of the implementations have been proposed by field programmable gate array (FPGA). This work analyses the very large-scale integration (VLSI) characteristics such as area utilization, power consumption and speed of operation of different types of implementation of Booth multiplication scheme. Based on the exhaustive examination on Booth multiplication scheme, it is noticed that the recent implementation of approximate computing-based and modified two’s complementor-based multiplication algorithms outperform other multiplication schemes. Further, the VLSI technology using ST Microelectronics (STM) 28 nm and TSMC 45 nm CMOS processes beat the other implantation schemes by providing less-area and power as well as high-speed of multiplication, respectively.