University of Bahrain
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Design of Serial Multiplier Circuit Based on a Variable Length Conditional Binary Counter for Improved Critical Path Delay and Slack Time

Show simple item record Gupta, Mangal Deep Chauhan, Rajeev 2021-07-25T08:40:48Z 2021-07-25T08:40:48Z 2021-07-25
dc.identifier.issn 2210-142X
dc.description.abstract In this paper, a variable-length conditional counter algorithm is proposed to count or add the partial products of serial multiplier circuits for minimizing computational delay. The proposed variable-length conditional counter enables optimizing critical path delay and improving its slack time at different input frequencies. The evaluation of the slack time of any circuit is essential to estimate the highest frequency of operation. In this work, the slack time of the proposed architecture is computed and compared with the related work. The result shows that slack time is higher as compared to the existing circuit, which implies that the proposed architecture of the serial multiplier operates at high frequency. The proposed variable-length conditional counter design and its serial multiplier architecture of 8, 16, 32 and 64-bit has been designed using Verilog HDL. The simulation of the proposed design has been done on the mentor Graphics EDA Tool. The physical layout design of the proposed 8-bit multiplier circuit using 180-nm CMOS technology is obtained in this work. en_US
dc.language.iso en en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-NoDerivatives 4.0 International *
dc.rights.uri *
dc.subject Variable-length conditional binary counter en_US
dc.subject Critical path Delay en_US
dc.subject Slack time en_US
dc.subject Multiplier en_US
dc.subject Semi-custom Layout en_US
dc.subject Verilog HDL en_US
dc.title Design of Serial Multiplier Circuit Based on a Variable Length Conditional Binary Counter for Improved Critical Path Delay and Slack Time en_US
dc.contributor.authorcountry India en_US
dc.contributor.authorcountry India en_US
dc.contributor.authoraffiliation Deoria road & MMMUT en_US
dc.contributor.authoraffiliation Madan Mohan Malviya Engineering College en_US
dc.source.title International Journal of Computing and Digital System en_US
dc.abbreviatedsourcetitle IJCDS en_US

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