FPGA Implementation of Prototype Filter Bank Multicarrier Modulator

Abstract

Filter Bank Multicarrier (FBMC) is an emerging modulation technique that employs pulse shaping for improved spectral properties. However, the implementation complexity of FBMC is higher than the currently adopted modulation techniques like the Orthogonal Frequency-Division Multiplexing (OFDM). In this paper, we present a hardware implementation of a prototype FBMC modulator on Field-Programmable Gate Array (FPGA) platform. The approach employs the Canonical Signed Digit (CSD) in the implementation of the array multipliers used in the shaping filter and the twiddle factors in Inverse Fast Fourier Transform (IFFT). The implementation of the IFFT follows the Split Radix (SR) algorithm and the shaping filter is implemented by the Frequency Spreading (FS) method. The overall structure of the modulator is built as a pipeline structure for higher speed performance. The system is built using Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) code that was compiled and downloaded on DE2-115 FPGA kit using Quartus II software.