High Speed Transform Coding on Chip for Wireless Video Surveillance Systems

Abstract

Streaming video quality dependents in part upon the video encoding process. The Frequency Domain Motion Estimation process is commonly used to accelerate the entire video encoding process. It is used to reduce the encoding time by increasing the Motion Estimation Time Saving. The Combinational Discrete Cosine Transform consumes most of the time of the Frequency Domain Motion Estimation video encoder. Its function is to generate four transform coefficients to be used by the Frequency Domain Motion Estimation process. Generating such transforms slows down the encoding speed. Consequently, Frequency Domain Motion Estimation may not be suitable for online video applications. Saving time in the Combinational-Discrete Cosine Transform generator will considerably speed up the Frequency Domain Motion Estimation process. This paper proposes a fast Combinational-Discrete Cosine Transform architecture. The proposed architecture achieves up to 50% and 39% savings in both area and power consumption, respectively, compared to recent state-of-the-art Combinational-Discrete Cosine Transform architectures. The proposed architecture can perform up to 60 fps motion estimation over a 4CIF video at 123.21 MHz when integrated in the frequency domain encoder. It can be generalized to be used even for higher video resolution transmission such as HDTV broadcasting and video surveillance systems.