Design And Implementation of RiCoBiT: A Structured and Scalable Architecture For Network On Chip Based Systems

Abstract

We are already in an era of a billion transistors on a silicon die. This was possible due to research advancement of silicon physics and process technology which enabled implementation of large, high performance, complex functionality. The backbone of any high performance computing system is the underlying interconnection network. Today’s, high performance systems are designed using network on chip. The design was realised by placing the different processing modules using various topologies like 2D mesh, torus. These existing interconnects limit itself in terms of performance and scalability. This paper discusses a new structured and scalable topology - RiCoBiT : Ring Connected Binary Tree in brief as an alternative along with its design and HDL implementation.