Redundancy Based Design and Analysis of ALU Circuit Using CMOS 180nm Process Technology for Fault Tolerant Computing Architectures

Abstract

As the technology entering into Nano dimensions, the manufacturing processes are becoming less reliable, that is drastically impacting the yield. Therefore, fault tolerant systems are becoming more important, particularly in safety-critical applications. In this paper, we present the design and analysis of 4-bit Arithmetic and Logical Unit (ALU) circuit designed using CMOS 180 nm process technology for fault tolerant computing architectures. As, ALU is a functional block of the Central Processing Unit (CPU) of a computer system. It is highly recommended that the ALU block must be fault free or fault tolerant one. In order to have high reliability and high up time of the system, we have used the classical Triple Modular Redundancy (TMR) technique in which three redundant subsystems are used in order to attain high reliability. We have achieved lower power dissipation with higher reliability of ALU circuit. The Voter Logic and Fault detection circuits are also designed and reported in this paper.