University of Bahrain
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Power Efficient Multiply Accumulate Architectures using Modified Parallel Prefix Adders for Low Power Applications

Show simple item record S, Rakesh Grace, K. S. Vijula 2020-07-01T22:50:47Z 2020-07-01T22:50:47Z 2020-07-01
dc.identifier.issn 2210-142X
dc.description.abstract This paper presents different power efficient multiply accumulate architectures based on modified parallel prefix adders. A general multiply accumulate unit consists of a multiplier, an adder and an accumulator. The multiplier used in this study is a Vedic multiplier and the parallel prefix adders that are brought into this research include Kogge Stone adder, Brent Kung adder, Han Carlson adder and Hybrid Han Carlson adder. The pre-processing and post-processing stages in those adders which mainly consists of exclusive OR operations are modified using a switch level model of the exclusive OR gate. The corresponding modified adder is also used in the Vedic multiplier for adding the partial products. The performance analysis of the different multiply accumulate models is done in terms of power and figure of merit. The proposed modified multiply accumulate units showed significant improvement in power consumption and figure of merit. The various architectures are designed using verilog hardware description language. The models are simulated and synthesized using Xilinx Vivado Design Suite 2015.2 for Artix-7 field programmable gate array family with xc7a100tcsg324-1 as the target device with -1 speed grade. en_US
dc.language.iso en en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-NoDerivatives 4.0 International *
dc.rights.uri *
dc.subject Brent Kung adder, Han Carlson adder, Hybrid Han Carlson adder, Kogge Stone adder, Multiply accumulate, Parallel prefix adder, Verilog HDL, Xilinx vivado design suite en_US
dc.title Power Efficient Multiply Accumulate Architectures using Modified Parallel Prefix Adders for Low Power Applications en_US
dc.type Article en_US
dc.volume 9 en_US
dc.issue 4 en_US
dc.pagestart 615 en_US
dc.pageend 623 en_US
dc.source.title International Journal of Computing and Digital Systems en_US
dc.abbreviatedsourcetitle IJCDS en_US

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