Analysis of Reliability for the Gate Level Fault Tolerant Design using Probabilistic Transfer Matrix method

Abstract

As semiconductor integrated circuits entered into nanometer dimensions, large variations of parameters and drastic reduction in reliability conditions of the constituent devices may be expected. On basis of these unreliable concerns, the research in fault analysis and development of fault tolerant design methodologies are the growing concern nowadays. Design and development of the fault tolerant model of the system/circuit include two major areas. First, types of fault and the level of fault occurrence at the input and output of the circuit. Second, the analysis of reliability for the logic circuit. The aim of this paper is to improve the reliability and fault tolerance level of the logic circuit by introducing gate level redundancy with respect to the occurrence of transient fault. Triple Modular Redundancy methodology is used to design the fault tolerant model that improves the reliability of the logic circuit. The proposed Probability Transfer Matrix (PTM) algorithm evaluates and compares the reliability of the logic circuit without redundancy and with redundancy by the analytical formulations. The results of circuit reliability with respect to the gate error probability has been simulated for the occurrence of transient faults for the proposed logic circuits. The results have shown better improvement in reliability and fault tolerance level of 0.7% for the proposed logic circuit using gate level redundancy.