Storing and retaining divider using BDD-based adder/subtractor circuit

Abstract

The BDD-based circuits are tree-structured and equally share the current/power in the cell, which gives reduced power dissipation reduced and increased speed. The proposed adder/subtractor circuits are designed and verified in this article using a Decision Diagram, which is implemented into a Retaining Array Divider (RAD) and Non- retaining Array Divider (NRAD) for 5G applications. The circuits are simulated and layouts tested using the Mentor graphics tool. The layout vs circuit schematic has been performed for the proposed adder-based RAD and NRAD and evaluated for the parameters of Chip area, propagation delay, and power dissipation. The results obtained are compared with the results of existing works by different. The proposed adder/subtractor circuits were designed using Silterra 0.13µm. The subtractor circuit is compared with the existing author circuit, which gives more than 95% improvement in Power dissipation and 17.39% improvement in propagation delay. Our proposed subtractor circuit has been designed with an inverter model, which occupies more area. The adder/subtractor circuits are further implemented in the retaining and non-retaining array divider circuits, giving better power dissipation with 36.02% than A,Arya et al. DAXD 99.79% and 99.74% than A.Arya et al. ADIV and ADIV6 divider model circuit. The propagation delay and area are improved by more than 80% in terms of delay and more than 14% in terms of area than the recent report designs.