Networks-on-Chip Architecture Customization using Network Partitioning: A System-Level Performance Evaluation

Abstract

Networks-on-Chip (NoC) design is a trade-off between cost and performance. To realize the best trade-off between these factors, researchers have recently proposed using network partitioning techniques to customize the NoC architecture according to the application requirements. In this paper, the impact of using partitioning on different NoC metrics; namely, power, area, and delay, is analyzed. We present a system-level methodology to evaluate the performance of using partitioning-based architecture customization techniques with NoC. Our methodology is applied onto synthetic traffic as well as a number of real NoC benchmarks with different number of cores. Finally, we mathematically formulate evaluation factors that could be used as measures of the enhancements achieved by using partitioning.