Packet-based Adaptive Virtual Channel Configuration for NoC Systems

Abstract

The escalating numbers of on-chip processing cores necessitate the introduction of a high performance and scalable communication backbone. In respond to this, Network on Chip (NoC) systems are introduced to play an important role in determining the performance and power of the entire chip. Specifically, Packet-based NoC is known as the most viable communication solution for the multi-core SoC of the future. In NoC design, the buffering organization directs the control of data flow as well as facilitates the use of Virtual Channels (VC). In terms of buffering, the VC mechanism is categorized into static and dynamic models. In dynamic VC mechanism, VCs employ a variable number of buffer slots according to the on-chip traffic. This feature of dynamic VC mechanism encourages us to introduce the Packet Based Virtual Channel (PBVC) approach. The idea is that a VC is reserved when a packet comes in a router, and released when the packet leaves the router. This prevents a VC to hold more than one packet that subsequently removes the Head-of-Line (HOL) blocking in NoCs. Our proposed technique is more suitable for dynamically allocated multi-queue (DAMQ) schemes. In these schemes, an input or output port comprises a centralized buffer whose slots are dynamically allocated to VCs in real-time and according to the traffic conditions. We introduce the architectural and structural details of our DAMQ buffer organization as well as the hardware that our approach imposes. The simulation results support the theoretical concepts of our proposed technique. The results of the hardware requirements for the proposed model are compared with the conventional models. The experimental results show that PBVC can improve the network latency by 40% and the network throughput by 23% on average as compared to the conventional designs for specific high HOL traffic.