Abstract:
Advance in VLSI technology has led to the emergence of
on-Chip Systems (SoC), where a complete system with a
large number of intellectual property cores can be
integrated onto a single silicon chip. The performance of
SoCs highly depends on the speed and efficiency of their
underlying communications subsystems. On-Chip
Network (NoC), have been suggested to overcome the
scalability problem found in traditional shared-bus
communication architectures. Intensive research studies
are conducted in an attempt to find the optimal networks
in terms of performance and cost such as power
consumption, and silicon area.
This special issue of International Journal of Computing
and Digital Systems (IJCDS) published selected papers
from the 2014 International Workshop on the Design and
Performance of Networks on Chip (DPNoC 2014),
August 17-20, 2014, Niagara Falls, Ontario, Canada. The
international workshop DPNoC'2014
(http://www.intnoc.org/) was organized