A Cost - Effective Programmable SoC for H.265/HEVC Full Search Motion Estimation using Xilinx ZYNQ-7 ZC706 FPGA

Abstract

A complete Full Search Motion Estimation Video system that can be adopted and integrated into H.264/AVC and H.265/HEVC standards. The proposed system reduces the computational complexity as well as hardware complexity. The overall data needed by this system is greatly reduced by using smart and efficient local memory that uses data reuse principle. All components of the proposed system are optimized, and so, the speed of the proposed Motion Estimation system is greatly improved. Both of the current block and the corresponding search area are loaded efficiently inside the Processing Element (PE). The search area is loaded horizontally from a local memory while the current block is loaded once from an external memory. The local memory is implemented using registers and the addressing issues are done using a simple counter. This guarantees a fast processing, regularity of the data flow, simplicity of the hardware design, and 100% utilization factor of all components of the proposed system. Additionally, there are no complicated addressing modes to read or write data to/from the local memory. The proposed architecture is implemented using Xilinx ZYNQ-7 ZC706 FPGA tool. For a search range of 32أ—32 and block size of 16x16, the proposed Motion Estimation system can perform motion estimation of HDTV video at 123.53MHz operating frequency and achieving two levels of data reuse.